1. Field of the Invention
The present invention relates to a phase-locked loop circuit, and more particularly to a phase-locked loop circuit incorporated in a clock-signal generator which is used for recording and reproducing data under the so-called sampled servo format system.
2. Description of the Prior Art
As shown in FIG. 1, the so-called servo regions i.e. pre-pit regions are previously formed along the respective track centers on an optical disc such as magneto-optical disc and DRAW (Direct Read After Write) disc. Each sector defined by the servo regions consists of 43 servo blocks each of which is composed of 2 servo bytes and 16 data bytes following to the servo bytes. Each of the servo bytes consists of: one pair of wobbled pits disposed in an offset manner with respect to the track center of the optical disc; and one clock pit following to the wobbled pits. In case that a data-detecting optical spot beam emitted from a pickup device of an optical disc recording/reproducing apparatus stays at the track center of the optical disc, there is no difference in light-volume of the light beams reflected at the wobbled pits. In contrast, in case that the data-detecting optical spot beam deviates from the track center of the optical disc, there appear some difference in the light-volume of the reflected beams at the pair of the wobbled pits, which difference depends on the direction and largeness of the deviation of the spot beam with respect to the track center. Consequently, a tracking error signal is produced in response to the difference of the light-volume reduction of the reflected light beam at the pair of the wobbled pits, which difference corresponds to a level difference in RF signal. The tracking error signal is kept during a scanning period of the data bytes following to the servo bytes.
The wobbled pits are spaced apart from each other by a predetermined circumferential distance along the track center, the circumferential distance being alternately increased and decreased at intervals of 16 tracks to make it possible to precisely count the number of tracks having been fast searched by detecting a difference in the circumferential distance. In this case, 16-track counting is conducted.
A trailing one of the pair of the wobbled pits is spaced apart from a clock pit in each of the servo bytes by a specific distance "D" which does not appear in the data bytes to make it possible to employ the specific distance "D" as a synchronizing signal. On the basis of the synchronizing signal having been detected, various kinds of timing signals are produced. The mirror surface area of the distance D, which is disposed in a position between the trailing one of the pair of the wobbles pits and the clock pit functions as a focus area usable for obtaining a focus-error signal, the focus-error signal being kept during a period of time for reading the data bytes following to the servo bytes.
In case that a 5-inch DRAW disc on which the servo bytes described above are prerecorded is rotated at a speed of, for example 1800 rpm, the clock pits produce an RF signal with signal edges appearing at repetition frequency of 41.28 KHz.
In the DRAW disc carrying the above-mentioned pre-pit regions, the data bytes are recorded in an area following to the area of the prerecorded servo bytes. Such data bytes having been recorded on the DRAW disc are reproduced by using a clock signal generated in a clock generator circuit shown in FIG. 2.
In FIG. 2, the RF signal derived from an optical disc (not shown) through a pickup device 1 is amplified through a head amplifier 2, and then supplied to a differentiating and edge detection circuit 3 which differentiates the RF signal and to detect an edge of the differentiated RF signal, so that the circuit 3 issues edge pulses "a" forming a pulse train as seen from FIG. 4A. The edge pulses "a" issued from the differentiating and edge detecting circuit 3 are supplied to a synchronization detector circuit 4 and to one of a pair of input terminals of an AND gate 5 simultaneously. On the other hand, a phase-locked loop circuit 6 issues a regenerative clock pulse "e" to the synchronization detector circuit 4 in which an interval between adjacent ones of the edge pulses "a" are measured by counting the regenerative clock pulses "e". When the thus measured value of the interval reaches a predetermined value, the synchronization detector circuit 4 issues a synchronization-detecting signal "b" to a gate pulse generator circuit 7 which is so constructed as to issue a clock gate pulse "c" with a predetermined pulse width upon the lapse of a predetermined period of time from when the synchronization-detecting signal "b" is issued to the circuit 7 in response to the regenerative clock pulse "e" issued from the phase-locked loop circuit 6. The clock gate pulse "c" issued from the gate pulse generator circuit 7 is supplied to the other of the pair of the input terminals of the AND gate 5, the other of the input terminals serving as a data-reading window.
As a result, the AND gate 5 issues an output signal to a phase comparator circuit 8 of the phase-locked loop circuit 6. In the phase comparator circuit 8, the edge pulse "a" corresponding to the clock pit having been extracted in the AND gate 5 is compared in phase with the regenerative clock pulse "e" to produce an output signal which is supplied to a low-pass filter (LPF) 10.
The low-pass filter (LPF) 10 has a construction as shown in FIG. 3, i.e., the LPF 10 is comprised of: resistors R.sub.1, R.sub.2 and R.sub.3 ; capacitors C.sub.1 and C.sub.2 ; and an operational amplifier.
The low-pass filter (LPF) 10 smoothes the above output signal and issues the thus smoothed output signal as a control signal voltage to a voltage-controlled oscillator (VCO) 11 which in turn issues a regenerative clock pulse signal "e" having a frequency of for example 11.1456 MHz, which pulse signal "e" corresponds to the control signal voltage in phase. The regenerative clock pulse signal "e" thus produced is then supplied to the phase comparator 8.
In the phase-locked loop circuit (PLL) 6 of the present invention having the above-mentioned construction, the level of the RF signal is decreased upon the passage of an area of a pit of the detecting spot when the optical spot beam emitted from the pickup device 1 scans the servo bytes of the optical disc. Consequently, as shown in FIG. 4A, the differentiating and edge detector circuit 3 issues the edge pulse "a" at a time when the optical spot beam scans a pit on the optical disc. When the interval of the adjacent edge pulses "a" coincides in length with the distance "D", the synchronization detector circuit 4 issues the synchronization-detecting signal "b". In response to such synchronization-detecting signal "b", the gate pulse generator circuit 7 issues the gate pulse "c" such as shown in FIG. 4B, which gate pulse "c" gates the clock edge pulse "d" corresponding to the clock pits of the optical disc. Both of the edge pulse "a" and the gate pulse "c" are supplied to the AND gate 5 to make it possible that the AND gate 5 serves as a reading window, whereby as shown in FIG. 4C only the clock edge pulse "d" is separated and supplied to the phase comparator circuit 8 of the phase-locked loop circuit 6, which clock edge pulse "d" serves as a phase sampling pulse corresponding to the clock pit of the optical disc.
As a result, the regenerative clock pulse "e" synchronized with the clock edge pulse "d" is produced in the phase-locked loop circuit (PLL) 6.
In general, noises caused by faults appearing in the optical disc and its clock pits cause some extraneous electrical disturbance to enter the phase-locked loop circuit (PLL) 6. In case that the regenerative clock pulse "e" varies in phase under the influence of such extraneous electrical disturbance, i.e., for example, in case that a clock pulse such as an input clock pulse P2 which has its time base varied and makes its phase to be outside of a linear property range .+-..alpha., for example, -.pi. to +.pi. of a phase comparator is supplied to the phase comparator an output signal of which periodically linearly increases with respect to a phase difference ".phi." as shown in FIG. 5, the phase-locked loop circuit for canceling the phase difference component can not correctly operate nor perform the rapid convergence to the stable operation. The linear property range means a range in which a linear relation between input and output signals is kept, in this specification.
As far as a delay of the input clock pulse is within the linear phase reference range .+-..alpha., that is, the reference input clock pulse appears at such a time position as shown by a phantom line P.sub.1 as shown in FIG. 5, the phase comparator circuit 8 issues a voltage "A" volts to cancel the extraneous electrical disturbance entered the phase-locked loop circuit (PLL) 6. On the other hand, in case that the input clock pulse appears outside of the linear phase reference range, for example, at such a position as shown by a phantom line P.sub.2, the phase comparator circuit 8 issues a voltage "B" volts which causes a voltage-controlled oscillator circuit (VCO) 11 to disadvantageously operate so as to increase the extraneous electrical disturbance.
On the other hand, a window width .+-..beta. of the data-reading window for extracting the clock edge pulse is identical with .+-..pi. in theory in case of no jitter. However, in actual case, since there is some jitter caused by a condition of eccentricity of the optical disc and a decrease in C/N, the window width .+-..beta. of the data-reading window is smaller than the above-mentioned value .+-..pi.. It is also necessary to position the regenerative clock pulse "e" within the window width .+-..beta. of the data-reading window, the regenerative clock pulse "e" being deviated in phase under the influence of the extraneous electrical disturbance.